SingleEndedSynIC - TioggleFlipFlop
Connection Diagram:
A | E_VB | ||||||
B | |||||||
C | F_OUT_HIGH | ||||||
G_VS | |||||||
D | H_OUT_LOW | ||||||
E | J_CSM | ||||||
J_CSP | |||||||
GND |
Connections(118) | Position | Remark |
J_CSP | Right | |
J_CSM | Right | |
H_OUT_LOW | Right | |
G_VS | Right | |
GND | Bottom | |
F_OUT_HIGH | Right | |
E_VB | Right | |
E | Left | |
D | Left | |
C | Left | |
B | Left | |
A | Left |
Parameters(6) | Default | Remark |
UVLO_OFF[V] | 7.9 | |
UVLO_ON[V] | 8.5 | |
ImaxEAoutputCurrent | 500uA | Maximum output current the Error Amplifier can deliver (ususlly around a couple of mA) [Ampere] |
DCgain[.] | 30000 | DC gain of the open loop Error Amplifier. (Around 100dB for a current mode controller) |
UnityBandWidth[Hz] | 1e6 | Band width of the Error Amplifier. At this frequency the gain equals 1. Specify in [Hz] |
BlankingTime[s] | 100n | Blanking time for synchronuous gates |
Function |
Status | Standard |
Select from | Components\Library\PowerConverters\SMPS\Control\CurrentMode |
See also
DualEnded, Oscillator, SingleEndedIC, SingleEndedMax50IC, TimerGate, TimerGateOscillator,