JK-FlipFlopPosEdgePC - JK-Flip-Flop, Positive Edge Triggerred, with Preset and Clear
Connection Diagram:
| PRESET | ||
| C |
| Q |
| J | QN | |
| K | ||
| CLEAR |
| Connections(7) | Position | Remark |
| QN | Right | Inverted Output |
| Q | Right | Output |
| PRESET | Top | Preset of the Flip Flop when Preset is HIGH |
| K | Left | Reset |
| J | Left | Set |
| CLEAR | Bottom | Reset of the Flip Flop when Clear is HIGH |
| C | Left | Clock |
| Parameters(0) | Default | Remark |
| Function | The JK-Flip-Flop changes state at the positive edge of the clock input | |
| Special | When Preset is HIGH, the output is set to 1. When Clear is HIGH, the output is set to 1. |
|
| Status | Standard | |
| Export of Embedded C Code | YES | |
| Select from | Components\Library\Control\Digital\FlipFlopPresetClear | |
See also
JK-FlipFlopNegEdgePC,