JK-MS-FLIPFLOP - Clocked Master Slave JK-Flip-Flop
Connection Diagram:
| C |
| Q |
| J | QN | |
| K | ||
| Connections(5) | Position | Remark |
| QN | Right | Inverted Output |
| Q | Right | Output |
| K | Left | Reset |
| J | Left | Set |
| C | Left | Clock |
| Parameters(0) | Default | Remark |
| Function | The Master-Slave JK-Flip-Flop is build from two clocked SR-Latches. | |
| Status | Standard | |
| Export of Embedded C Code | YES | |
| Select from | Components\Library\Control\Digital\FlipFlops | |
See also
D-FlipFlop, D-FlipFlopNegEdge, JK-FlipFlop, JK-FlipFlopNegEdge, JK-FlipFlopPosEdge, SR-MS-FlipFlop, T-FlipFlop,