JK-FlipFlop - JK-Flip-Flop
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Connection Diagram:
C | ![]() | Q |
J | QN | |
K | ||
Connections(5) | Position | Remark |
QN | Right | Inverted Output |
Q | Right | Ouput |
K | Left | Reset |
J | Left | Set |
C | Left | Clock |
Parameters(0) | Default | Remark |
Function | The JK-Flip-Flop is build from one clocked SR-Latch. |
Status | Standard | |
Export of Embedded C Code | YES |
Select from | Components\Library\Control\Digital\FlipFlops |
See also
D-FlipFlop, D-FlipFlopNegEdge, JK-FlipFlopNegEdge, JK-FlipFlopPosEdge, JK-MS-FLIPFLOP, SR-MS-FlipFlop, T-FlipFlop,