JK-FlipFlopPosEdge - JK-Flip-Flop, positive Edge Triggerred
Connection Diagram:
| C |
| Q |
| J | QN | |
| K | ||
| Connections(5) | Position | Remark |
| QN | Right | Inverted Output |
| Q | Right | Ouput |
| K | Left | Reset |
| J | Left | Set |
| C | Left | Clock |
| Parameters(0) | Default | Remark |
| Function | The JK-Flip-Flop changes state at the positive edge of the clock input | |
| Status | Standard | |
| Export of Embedded C Code | YES | |
| Select from | Components\Library\Control\Digital\FlipFlops | |
See also
D-FlipFlop, D-FlipFlopNegEdge, JK-FlipFlop, JK-FlipFlopNegEdge, JK-MS-FLIPFLOP, SR-MS-FlipFlop, T-FlipFlop,