SR-MS-FlipFlop - Clocked Master Slave SR-Flip-Flop
Connection Diagram:
C | Q | |
R | QN | |
S | ||
Connections(5) | Position | Remark |
S | Left | Set |
R | Left | Reset |
QN | Right | Inverted Output |
Q | Right | Output |
C | Left | Control |
Parameters(0) | Default | Remark |
Function | The Master-Slave SR-Flip-Flop is build from two clocked SR-Latches. |
Status | Standard | |
Export of Embedded C Code | YES |
Select from | Components\Library\Control\Digital\FlipFlops |
See also
D-FlipFlop, D-FlipFlopNegEdge, JK-FlipFlop, JK-FlipFlopNegEdge, JK-FlipFlopPosEdge, JK-MS-FLIPFLOP, T-FlipFlop,