Gate Driver
There are various ways to model a gate driver in Caspoc. We will start with a very simple model to explain the basics and proceed up to a complete driver model and detailed Mosfet model.
Basic Gate driver
To create a simple gate driver, we need to do the following four parts, shown as below: (1) Build the half bridge inverter using two ideal Mosfets from the components/circuit/semiconductor/Mosfet. Add freewheeling diodes from components/circuit/semiconductor/D. These Mosfets have a block diagram input and are ideal switches. (2) add the RL load and the voltage sources. (3) Create a zero reference by adding the ground symbol components/library/electric/ground/ground between the two voltage sources. This makes the positive and negative DC link voltage. (4) Add the basic block-diagram blocks TIME and SIGNAL from components/blocks/source for building a square wave that will control the gates of the Mosfets. Use the LIM block from components/blocks/nonlinear to create the high and low gating signal.
In the above simulation there is no blanking time between the Mosfets. The voltage at node sw becomes a pure square wave with a frequencyu of 20kHz and a dutycycle of 0.7. We used a single input voltage sensor components/library/sensor/voltage/v to measure the voltage on node sw to display it in the scope. This voltage is measured with reference to the ground node.
Adding Blanking Time
To include blanking time, a dual output pwm genertor was used that has some blanking time between the gate signals.
In this example we used the obsolete blocks from library/control, which are replaced by the block DoubleEnded and BlankingTimeGate from the components/library/PowerConverters/SMPS/PWM library
Specifying Ton and Toff delay
The blanking time only specifies a delay between turn on and turn off. However, in reality there are two different time delays for turn on and turn off. These are modelled using the TurnOnTurnOff block TonToff. The input pt this block is a square wave signal being the basic control signal for the inverter leg. The outputs are delayed by Ton and Toff for turning on and turning off. A turn on delay of 650ns and a turn off delay of 150ns is specified here.
The voltage at node sw typically shows the difference between the voltage drop over the synchronous Mosfet and freewheeling diode. During blanking time, the freewheeling diodes are conducting.
Adding a gate charge model.
The gate charging delay depends on the required gate charge and the gate resistance. Use is made of the level0 Mosfet model components/library/Semiconductors/Mosfet/nMosfetLevel0. The gate of this model includes the gate capacitance CGS and the internal gate resistance RG. Also the gate threshold voltage Vth is modelled. The gate is not a block diagram node any more, but a circuit node and needs to be driven from a voltage source. Here we use a controlled voltage source B selected from components/circuit/Controlled Sources/B and use a GAIN block from components/blocks/math for multiplying the gating signal from the TurnOnTurnOff block TonToff with 15 to get a realistic gating voltage.
The delay caused by the gate charging is now added and the extra delay can be controlled by selecting a proper gate resistance. In this simulation we used a typical value of 10 ohms.
Gate driver totem-pole
The gate charging voltage is not so ideal and constant as in our previous example. This can be modelled by adding the gate driving totem-pole circuit to control the charging and discharging of the gate capacitance. The delay from the Turn-On Turn-Off block TonToff is now extended with the delay caused by charging the gate capacitance CGS with a time constant τ=(RGateRGInternal)*CGS
The scopes scope1 and scope2 show the voltage at the gate at the low side and the gate charging current for the high side. We are however still using a constant infinite voltage to drive the gates.
Adding the Bootstrap capacitor
To get a more realisitic value for the gate voltage forthe high side Mosfet a Bootstrap circuit is added. The low side Mosfet is directly fed from the constant volage source of 15 volts. The high side Mosfet gate voltage is creating by using the bootstrap capacitor C1. It is charged each time the low side Mosfet is conducting. It is therefore important that the low side Mosfet is switching regularly, otherwise the bootstrap capacitor C1 does not get charged.
The gate driver has a smal internal resistance which is not of large influence. More important is the driving voltage for the high side Mosfet. The bootstrap capacitor C1 swings with the voltage at node sw and will only charge when node sw gets close to the minus DC link voltage
Using the Gate driver IC
The gate driver contains a number of components and at this point it is better to replace those by a model of a gate driver. Here we use the IR2111 model as it allows control from a single control signal and includes high side gate driving and has internal different gate delays for turning on and turning off. The bootstrap capascitor C1 is placed at the right side of the IC and connected to the pin VS of the IC which is the voltage level that swings during switching. A resistor of 1 &Ohm; is added in series with the bootstrap diode which prevents large current spikes when the diode D1 starts conducting.
The voltage levels of the gates Vhigh and Vlow are displayed in the first scope. Her you can see that they are not fully equal any more, as the voltage for the high side has to be charged up by the bootstrap capacitor. Only after a number of cycles both Vhigh and Vlow are becoming equal. The supply voltage for the IC is directly connected to pin 1 called Vcc. Internally this voltage is used for the low level totem pole. Both totem pole circuits are only operating if their supply voltage is at the required level, as indicated by the blocks UVLO (Under Voltage Lock Out). A high input impedance buffer and a voltage level shift distribute the incoming control signal at pin 2 IN to the gate drivers.
Gate Driver IR2111 in DIP package
Instead of using a detailed symbol for the gate drive, the same functionality is available in a smaller size model. Here the same components are packed inside a DIP-8 compatible layout.
Functionality is the same as with the previous model. Notice the layout of the DIP package for connecting the Mosfet gate to the IC. Short wires are possible and the pins forh te high side are located in correct order on one side of the IC. This enables short wire loops on the PCB to keep loop inductance at minimun. You can however at loop inductance in the gate circuit loop by adding small inductances, for example 5 to 100nH in the gate loop circuit. These inductances(not implemented in the above model) will influence the gate charging dynamics considerably.
More detailed Mosfet model
The gate driver IC is not supplied from a infinite constant voltage but is coming from a small power supply which uses capacitors to stabilize the voltage level. Care has to be taken that these capacitors have an internal Equivalent Series Resistance [ESR] which affect the voltage level.The effect of this is clearly visible in the gate voltages Vhigh. However a closer examination reveals a stranger difference between Vhigh and Vlow. This has to do with voltage ringing on node sw.
In order to understand what is happening at node sw, we need a more detailed Mosfet model, see components/library/Semiconductor/Mosfet/TrenchMosfetDiode. The here applied model includes the feedback and output capacitance of the Mosfet. Secondly the non-linear relation between VGS, VDS and IDS as function of temperature is included in this model. This model is used to study the turn on an turn off of the Mosfet in detail. In includes the antiparallel diode that is modelled to show reverse recovery. Because the non-linear relation between VGS, VDS and IDS is a function of temperature, a thermal model has to be added to the Mosfet. This is done using the TO220 thermal case model fro the thermal library components/library/thermal/case. The temperature of the case can be monitored at hte thermal node between the Mosfet and the thermal case node. The conduction and switching losses of the Mosfet are flowing out of the Mosfet into the thermal case model, thereby heating up the case en eventually also the die of the Mosfet.
The voltage ringing at node sw is now clearly visible in scope6. Scope4 shows the voltage of the low-side Mosfet and the current through the low-side Mosfet.
Switching waveforms
The ringing at node sw is most prominent during turn on of the high side Mosfet. This has to do with the reverse recovery of the low side antiparallel diode and the size of the parasitic inductance between Mosfets.
Mosfet overshoot voltage
The voltage over the low side Msofet is displayed below. Here it is visible that due to ringing on node sw, the voltage over the low side Mosfet reaches around 30 volts, being 50% more than the DC link voltage
From the above waveform we can see a ringing with a frequency equal to 1/50ns = 20Mhz = 1/ (2 π √(LCDS)). This account approximately to the output capacitance of the low side Mosfet and the parasitic inductance.
The voltage on the bootstrap capacitor is nearly constant, even during the ringing of node sw.
The bootstrap capacitor has to provide the current for the gate charging. This is clearly visible in the figure below. The gate charge currents (red and blue traces) have a peak of over 1 ampere. This current is provided by the bootstrap capacitor. Charging of the bootstrap capacitor takes place as soon as the low side Mosfet is conducting. At this moment a peak current through the series bootstrap diode flows, charging the bootstrap capacitor(light-blue trace).
The samples from this tutorial can be downloaded from this link.