inter6 - Logic Delay

preview

Connection Diagram:

CLOCK G1H
D
G1L
G2H
G2L
G3H
G3L
G4H
G4L
G5H
G5L
G6H
G6L

Connections(27)PositionRemark
G6L Right
G6H Right
G5L Right
G5H Right
G4L Right
G4H Right
G3L Right
G3H Right
G2L Right
G2H Right
G1L Right
G1H Right
D Left
CLOCK Left

Parameters(0)DefaultRemark

Function Delay block for delaying a gate control signal.

Status Standard
Export of Embedded C Code YES

Select from Components\Library\PowerConverters\SMPS\PWM

See also
BlankingTimeGate, ConstantPWM, DoubleEnded, Interleaved, Interleaved6, LLC, MODE, PhaseShifted, PhaseShiftedPWM, PWM, SingleEnded, Synchronous,
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