JK-MS-FLIPFLOP - Clocked Master Slave JK-Flip-Flop

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Connection Diagram:

C Q
JQN
K

Connections(5)PositionRemark
QN Right Inverted Output
Q Right Output
K Left Reset
J Left Set
C Left Clock

Parameters(0)DefaultRemark

Function The Master-Slave JK-Flip-Flop is build from two clocked SR-Latches.

Status Standard
Export of Embedded C Code YES

Select from Components\Library\Control\Digital\FlipFlops

See also
D-FlipFlop, D-FlipFlopNegEdge, JK-FlipFlop, JK-FlipFlopNegEdge, JK-FlipFlopPosEdge, SR-MS-FlipFlop, T-FlipFlop,
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