D-FlipFlop - D-FlipFlop Positive Edge Triggered

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Connection Diagram:

C Q
DQN

Connections(4)PositionRemark
QN Right Inverted Output
Q Right Output
D Left Data
C Left Clock

Parameters(0)DefaultRemark

Function The D-Flip-Flop changes state at he positive edge triggering of the clock input C.

Status Standard
Export of Embedded C Code YES

Select from Components\Library\Control\Digital\FlipFlops

See also
D-FlipFlopNegEdge, JK-FlipFlop, JK-FlipFlopNegEdge, JK-FlipFlopPosEdge, JK-MS-FLIPFLOP, SR-MS-FlipFlop, T-FlipFlop,
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