JK-FlipFlopNegEdgePC - JK-Flip-Flop, Negative Edge Triggerred, with Preset and Clear

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Connection Diagram:

PRESET
C Q
JQN
K
CLEAR

Connections(7)PositionRemark
QN Right Inverted Output
Q Right Output
PRESET Top Preset of the Flip Flop when Preset is HIGH
K Left Reset
J Left Set
CLEAR Bottom Reset of the Flip Flop when Clear is HIGH
C Left Clock

Parameters(0)DefaultRemark

Function The JK-Flip-Flop changes state at the negative edge of the clock input
Special When Preset is HIGH, the output is set to 1.
When Clear is HIGH, the output is set to 1.

Status Standard
Export of Embedded C Code YES

Select from Components\Library\Control\Digital\FlipFlopPresetClear

See also
JK-FlipFlopPosEdgePC,
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